1. Field of the Invention
The present invention generally relates to static random-access memory (SRAM), and, more specifically, a technique for improving SRAM sense amplifier voltage differential.
2. Description of the Related Art
A conventional SRAM module typically includes a collection of bit cells, where each bit cell is configured to store a logical value (e.g., a “0” or a “1”). During a read operation, a given bit cell outputs two voltage signals on two corresponding bit lines. Each bit line is coupled to a different p-type metal-oxide-semiconductor (PMOS) within an input/output (I/O) circuit residing downstream of the bit cell. The SRAM module causes the I/O circuit to sample the two voltage signals by asserting a column select signal to the two PMOSs. In response to the column select signal, each PMOS conducts a voltage to a sense amplifier also residing within the I/O circuit. The sense amplifier is configured to receive the voltage output by the PMOSs by way of two sense nodes, each coupled to a different one of the PMOSs. The sense amplifier measures the voltage differential between the two sense nodes and, based on the measured voltage differential, determines whether the bit cell output a “0” or a “1.” This approach relies on a technique known in the art as “differential signaling.”
One weakness of the approach described above is that the sense amplifier requires a large voltage differential between the sense nodes in order to accurately and quickly determine whether that differential represents a “0” or a “1.” However, the voltage differential between the sense nodes, and therefore the read accuracy and speed of the I/O circuit in general, is sensitive to several factors. First, the PMOSs each cause a voltage drop from the corresponding bit lines, respectively, to the downstream sense nodes. That voltage drop degrades the voltage differential between the sense nodes. This issue is compounded by the fact that manufacturing differences across PMOSs may introduce unpredictable voltage drops across different PMOSs. Second, the supply voltage to the I/O circuit is continuously reduced over each development cycle, thereby decreasing the initial voltage differential between the bit lines and, in turn, the voltage differential between the sense nodes. In sum, the read accuracy and speed of conventional I/O circuits is limited by the voltage differential detected at the sense nodes of the sense amplifier.
Accordingly, what is needed in the art is a more effective technique for generating a voltage differential at the sense nodes of a sense amplifier.